The present invention relates generally to the manufacture of integrated circuits, and more specifically to methods and apparatus for efficiently combining an extensive logic circuit with a large memory circuit.
Logic circuits and memory circuits are typically manufactured with different processes designed to optimize these respective circuit types. For example, a memory circuit, such as a DRAM, is typically optimized by using a low leakage but also low performance transistor and special high density storage capacitor elements interconnected with two layers of metal. Conversely, logic circuits tend to be optimized when constructed with higher performance transistors and minimized capacitance. Also, logic circuits typically include more than two layers of metal.
It is possible to create a memory circuit with a logic circuit process, however the resulting circuit would not be optimized for the memory function. Typically, DRAM is created by a logic process that has about 1/8 to 1/10 the density and a shorter data retention time than that which is achievable with a DRAM process. Conversely, it is also possible to create a logic circuit with a DRAM process, however the logic circuit will typically be about 1/4 the density of that achievable with a logic process.
FIGS. 1a and 1b illustrate the inefficiencies encountered in the prior art of combining memory and logic circuits together utilizing a single process. FIG. 1a depicts a typical hybrid integrated circuit 10 manufactured with a logic circuit process combining a memory circuit 12 and a logic circuit 14 on a single substrate surrounded by a number of bonding pads 16. Similarly, FIG. 1b depicts a typical hybrid integrated circuit 20 manufactured with a memory circuit process combining a memory circuit 22 and a logic circuit 24 on a single substrate surrounded by a number of bonding pads 16.
Assuming that both integrated circuits 10 and 20 represent the same amount of memory and logic circuitry, the inefficiency of the non-process related circuitry is represented by the differences in area occupied by the circuitry. For example, the area required for memory circuit 12, created with a logic process, is much greater than the area required for memory circuit 22, created with a memory process. Likewise, the area required for logic circuit 24, created with a memory process, is much greater than the area required for logic circuit 14, created with a logic process.
For logic circuits that do not require a large memory capability, e.g., only a few kilobytes of memory, the logic process may suffice for both the logic and memory functions. Similarly, for memory circuits that require only a small logic capability, for example an input/output capability, the memory process may suffice for both the memory and logic functions. However, for circuits that require both a large memory capability and an extensive logic capability, neither the memory nor logic processes are adequate for effectively producing both memory and logic circuits.
For example, NeoMagic of Santa Clara, Calif. has produced a hybrid graphics chip under the trademark MagicGraph NM2070 using a 16M DRAM process to implement both logic and memory on a single chip. This costly approach appears technically adequate so long as the logic complexity is low in comparison to the memory size. However, a device such as this would likely be less than optimal whenever the logic complexity is high relative to the memory size.
In typical applications large memories and large logic circuits are configured as discrete parts. For example, separate memory chips are often configured to act as a frame buffer for a logic circuit. However, by separating memory and logic functions, device count is increased, circuit board size is increased, and performance issues due to increased pin counts and interconnections tend to increase. Performance is further limited by the typically narrow-word interfaces to the memory circuit, such as the 32-bit wide interface typically found in notebook computer systems and the 64-bit wide interface found in some desk-top computer systems. For memory intensive applications, such as 3D graphics rendering applications, the narrow-word interface of a conventional separate frame buffer tends to increase both the complexity and cost of the system.
In view of the foregoing, what is desired are methods and apparatuses capable of efficiently combining an extensive logic circuit with a large memory circuit in a single device.